Magma® Design Automation announced that ClearSpeed Technology completed a 90-nanometer (nm) design using Hydra^TM, Magma's new automated floorplan synthesis and hierarchical design planning product. ClearSpeed, noted for delivering power-efficient, high-performance processors, used Hydra to design a processor for massively parallel compute applications in scientific, financial and embedded markets.  One of the panels of the multicore chip contains 3.6 million standard cells and nearly 500 hard macros.

Hydra's intuitive, auto-interactive capabilities enabled ClearSpeed to develop a final floorplan more quickly. Using Magma's Relative Floorplanning Constraints^TM, the designers were able maintain the placement of associated objects and specify which parts of the floorplan to maintain while continuing to optimize the rest.  ClearSpeed has long partnered with Magma on 130- and 90-nm processor designs. ClearSpeed has already begun using Hydra its next-generation processor that will be implemented in 45-nm technology. With Hydra's black-box technology, the designers have been able to start making decisions on the floorplan of this 30-million cell design using just the top-level netlist. ClearSpeed will complete the design using the entire Magma Talus® IC implementation suite and Quartz^TM timing and extraction software for sign-off.

Hydra can be used in third-party flows or integrated with Magma's Talus IC implementation system.  Used in conjunction with Talus Design or Talus Vortex, Hydra offers seamless integration from prototyping to implementation within the same data model.  Hydra is seamlessly integrated with RioMagic^TM, Magma's package-aware chip planning solution, enabling early I/O planning and placement tradeoffs for both peripheral and flip-chip packages and full-chip DRC-clean 45-degree redistribution layer (RDL) routing.

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