eInfochips announced the availability of OVM & AVM
3.0-compliant AMBA AHB SystemVerilog
Verification component. This integration which is a result of a collaborative
effort between Mentor Graphics and eInfochips will enable designers to more
effectively use key SystemVerilog functionality, and drastically reduce
verification cycle times for designs that incorporate standard interfaces such
as AMBA. AMBA AHB verification IP provides necessary building blocks for
efficient design-under-test (DUT) for module and system-level verification,
including comprehensive assertion testing.
eInfochips' AMBA AHB verification component is based
on AVM 3.0 ~ OVM that allows coverage driven verification suitable for
verifying Master, Slave and AHB with
various combinations. The AHB SV VIP provides all the necessary building blocks
to test master/slave DUT with the AHB protocol. The verification component can
be easily configured Master, Slave and AHB and allows Module & System-level
verification. It integrates advanced verification techniques like
constrained-random stimulus, functional coverage and assertions into a single transaction
level modeling (TLM)-based framework implemented in both SystemC and
SystemVerilog in the AMBA AHB VIP, apart from improved management and reporting
features and more top-level environments for integrating 3rd-party IP Cores.
For more info please visit http://einfochips.com/services/OVM_IP.html
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